data brief for further information contact your local stmicroelectronics sales office. october 2011 doc id 022309 rev 1 1/4 4 STIH207 advanced dual hd avc processor with integrated low power standby controller features st40 applications cpu with 256 kb l2 cache 32-bit lmi supporting ddr2/ddr3 decoding of h264, mpeg 2, vc-1 and avs hd video streams decoding of 1080p60 avc, dual hd avc and mvc shp video streams 3dtv decoding and display compatible with hdmi 1.4a extensive connectivity (2 usb 2.0 ports; ethernet mii/rmii/tmii port; sd/mmc card port; esata port; pcie) secure booting from slc nand flash or serial nor flash; emmc booting option low-power process and architecture integrated low power standby controller high-quality video resizing and de-interlacing integrated ethernet phy description the STIH207 uses the latest process technology to provide a cost-effective, feature rich, highly integrated soc for set-top boxes (stbs). it is targeted at the advanced decoding stb market across all networks (cable/satellite/dtt/x-dsl/ip) worldwide and is suitable both for operator markets (with advanced security) and retail markets. the STIH207 provides a solution for operators and manufacturers to specify a range of cost- effective, high performance stbs including basic zappers, interactive stbs, ip clients, and dvr stbs with content delivery possible using broadcast or broadband networks or both (hybrid stbs). jtag stb peripherals i/o resets analog out clocks modes pcm i/o s/pdif out external interrupts peripherals smartcard connectivity transport security analog video audio i/o display video i/o transport streams parallel/serial in/out audio decoder st231 cpu video decoder emi spi system interfaces cpu/fpu stbus pcm players pcm reader dacs slc nand flash ddr3 lmi esata/pci-e ethernet sd-mmc/sdio dual usb key scan clock gen system serv dual fdma l2 cache serial flash ci-plus cards ddr2/ddr3 ssc uart rtc pwm gpios ir/uhf low power standby controller hdmi www.st.com
introduction STIH207 2/4 doc id 022309 rev 1 1 introduction the STIH207 offers current users of st?s growing family of advanced decoding ics enhancements in performance and features, enabling operators to offer consumers new multimedia-rich services and viewing experiences, including new 3dtv features. faster ddr3 memory is also supported, and the applications cpu benefits from an l2 cache. the STIH207 keeps pace with the latest advanced security requirements of the main ca vendors, and an integrated standby controller enables the STIH207 to target stringent low power regulations. features benefits st40 applications cpu, with 32ki and 32kd l1 caches and 256k l2 cache. high performance processing up to 1020 dmips (1) for applications and middleware. 1. frequency for extended mode to be confir med after silicon characterization. integrated low power standby controller within its own power island. secure hibernation to, and fast resume from, very low power passive standby mode, targeting stb standby power < 0.5 w. latest generation of st's delta video decoder with an st231-based multi-codec capable controller, coupled with a high quality video display pipeline (hqvdp). decoding of advanced high definition standards (mpeg2, h264, vc-1, avs) plus the performance and flexibility for web-bas ed content decoding such as flash ? , divx?, mjpeg and real ? , without impacting applications cpu performance. dual usb 2.0 hosts, esata, ethernet mac with mii/rmii/tmii interfac es, pci-e, sd-mmc/sdio interface. extensive high speed connectivity for the widest range of stb peripherals, such as flash drives, external hdds, ethernet, home network controllers (such as moca ? , wi-fi), docsis ? modem and memory cards. decoding of 1080p60 avc, dual hd avc and mvc shp video streams. enables advanced high-definition viewing experiences including full resolution per eye 3dtv, full-hd 2d services and hd picture-in-picture support (hd-pip). nocs1.0/1.1/1.2/3.0, nsk2.0 and dvb-csa3 ready. fully compliant with the latest advanced security requirements of ca vendors.
STIH207 revision history doc id 022309 rev 1 3/4 2 revision history table 1. document revision history date revision changes 24-oct-2011 1 initial release.
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